Circuit for Locking of a Test Bus

Publication Number: SI21978A
Application Date: 20. 1. 2005
Assignee/Applicant: Jožef Stefan Institute [SI]
Inventor: Anton Biasizzo, Franc Novak
Title: Vezje za zaklepanje testnega vodila [SL], Circuit for Locking of a Test Bus [EN]
Description: The subject of the submitted invention is a circuit for locking a test bus within electronic circuits, which include a test bus, designed according to the IEEE 1149.1 or IEEE 1149.4 standards. The circuit for locking a test bus is used for preventing access to electronic circuits and systems during their standard operation via the existing testing infrastructure, which include a test bus designed according to the IEEE 1149.1 or IEEE 1149.4 standards. The circuit for locking of a test bus, which consists of a circuit for decoding test commands (1), a multiplexer (2), a register for entering locks and keys (3), a key register (4), a lock register (5) and a comparator (6) is characterised by the fact that the circuit for decoding of test commands (1) decodes two new commands: UNLOCK and LOCK while generating control signals (22), (23), (24), and (25) accordingly.
Drawings:
Category: Electronics, IT and Telecommunications
Technology application codes: Electronics, IT and telecoms
Market application codes: Other electronics related
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